The recent literature has emphasized "one-device" memory cell arrangements where higher and higher degrees of integration are being sought. This is achieved in most cases by juxtaposing access transistors and storage capacitors to achieve cell area reduction while at the same time increasing the storage capacitance. In the prior art, capacitance is increased by decreasing oxide thickness, increasing the surface capacitor area or forming trench capacitors in semiconductor substrates.
In a co-pending application, assigned to the same assignee as the present application, Ser. No. 620,667, filed June 14, 1984, a DRAM cell is shown wherein a trench capacitor extends into a heavily doped substrate which acts as the counterelectrode of the capacitor. In addition, an FET access transistor is disposed adjacent the trench capacitor and has its source/drain directly connected to the electrode of the trench capacitor disposed in the trench. In the embodiment shown, the access transistor is electrically isolated from other similar cells and from the highly doped substrate by insulation. The application doesn't address the fabrication of such DRAM cells in the CMOS environment wherein the access transistor of the cell is formed within a well disposed in a semiconductor region of opposite conductivity type. To the extent that the structure of the present application incorporates such a well and further incorporates a trench capacitor which penetrates or extends through the well to a heavily doped portion of the substrate, the present application distinguishes over the structure of the above mentioned co-pending application.
An article entitled "Novel High Density, Stacked Capacitor MOS RAM" by M. Koyanagi et al, Proceedings of the 10th Conference on Solid State Devices, Tokyo, 1978; Japanese Journal of Applied Physics, Supplement 18-1, pp. 35-42 describes a Dynamic Random Access Memory (DRAM) cell using a capacitor stacked on top of an associated access transistor. The structure is of interest because the source of the access transistor is directly connected to one electrode of the capacitor. There is, however, no mention of a trench capacitor or any indication that a trench capacitor may be used in conjunction with an access transistor which is disposed in an n or p-well.
An article entitled "A Corrugated Capacitor Cell (CCC) for Megabit Dynamic MOS Memories" by H. Sunami et al, IEEE Electron Device Letters, Vol. ED6-4, No. 4, April 1983, pp. 90-91, shows a one-device memory cell which is characterized by an etched-moat storage capacitor which extends into the substrate. Structurally, the storage capacitor is disposed alongside an access transistor. The moat is insulated and filled with polysilicon to form one plate of the capacitor. Because a depeletion region is formed in the semiconductor substrate around the moat, when a positive potential is applied to the polysilicon capacitor electrode, a minimum spacing between moats is required to prevent punch-through. This fact militates against denser packing of devices. Also, in order to form an inversion region in the substrate which acts as a storage electrode, the substrate must be p.sup.- -conductivity type, suggesting that the authors contemplated neither the use of a substrate as a common counterelectrode nor the penetration of a well by a trench into a highly doped region to obtain the bulk of their capacitance. In the structure of the present application, at least a portion of the substrate must be highly doped to provide a counterelectrode for all the DRAM cells formed on a chip. No short circuiting of the capacitors occurs because the storage electrode is disposed in the trench and insulated from the counterelectrode. In addition, from a structural point of view, there is no direct connection in the reference between a source/drain diffusion and the polycrystalline material disposed within the moat and no access transistor disposed in a well.
An article entitled "A Submicron CMOS Megabit Level Dynamic RAM Technology Using Doped Face Trench Capacitor Cell" by K. Minegishi et al, IEDM 83, December 1983, pp. 319-322 discusses RAM cells in the CMOS environment and shows a trench the wall of which is heavily doped to form an extended source/drain region for an associated access transistor. A polycrystalline electrode is disposed in insulated spaced relationship with the substrate within the trench which acts as the counterelectrode of the capacitor. In this article, the substrate doesn't act as a counterelectrode inasmuch as a highly doped substrate would degrade the performance of associated transistors. In any event, the capacitor doesn't penetrate a well region and there is no direct connection between the source of the access device and the electrode in the capacitor trench.
U.S. Pat. No. 4,397,075 filed July 3, 1980 shows a one-device memory cell where enhanced capacitance is obtained by extending the drain diffusion into a well etched in the semiconductor substrate. There is no separate capacitor element and the capacitance enhancement is a direct result of increasing the drain p-n junction area.
U.S. Pat. No. 4,327,476 filed Nov. 28, 1980 shows a one-device memory cell which incorporates a capacitor electrode disposed in a groove or trench. The electrode is formed alongside a source/drain region and in insulated spaced relationship with the substrate. There is no interconnection between the capacitor electrode in the trench and the source/drain region. The reference doesn't show the use of a well or a trench which penetrates into a highly doped substrate portion.
An article in the IBM Technical Disclosure Bulletin entitled "Very Dense One-Device Memory Cell" by C. G. Jambotkar, Vol. 25, No. 7, July 1982, p. 593, shows a one-device memory cell wherein the drain diffusion is formed around the periphery of a trench. The inside of the trench is covered with insulation and the remaining void may be filled with polyimide, polysilicon or SiO.sub.2. While a trench is formed for the cell shown, no separate capacitor is formed therein. The structure shown does no more than lengthen the drain diffusion to thereby increase the junction capacitance.
From all the foregoing, it should be clear that none of the above cited references provides a memory cell wherein both the access transistor and its associated trench capacitor are formed in a well disposed in an opposite conductivity type substrate. As a result, prior art structures incorporating a well are limited as to the amount of capacitance which can be obtained because it was not perceived that the trench could penetrate through the well and achieve most of the capacitive effect in the heavily doped counterelectrode portion of the substrate. Thus, none of the references cited shows the combination of the access transistor and trench capacitor disposed in a well where the trench capacitor extends from the well or penetrates through the well to a highly doped substrate and wherein the source of the access transistor is directly connected to the electrode disposed inside the trench.
It is, therefore, a principal object of the presnet invention to provide a "one-device" DRAM cell wherein both an access transistor and its associated trench capacitor are formed in a well in a semiconductor substrate.
Another object is to provide a DRAM cell wherein the depth of the trench capacitor is greater than the depth of a well in which as associated transistor is formed.
Another object is to provide a DRAM cell wherein a trench capacitor extends from a well into a highly doped substrate wherein the greatest portion of the capacitance of the cell is obtained.
Still another object is to provide a DRAM cell wherein the capacitance obtainable is greater than that obtained using prior art approaches.
Yet another object is to provide a DRAM cell which is not subject to punch-through between adjacent capacitor trenches and is less subject to alpha particle induced soft errors inherent in memory cells which use relatively high resistivity substrates.
Yet another object is to provide a DRAM cell which is less susceptible to soft errors due to minority carrier injection from peripheral circuits.